Failure analysis of integrated circuits is required to identify the root causes of product failures that occur during manufacture, technology evaluations and in end user systems in the field. The results of this analysis are used to drive technology, product design, and test enhancements which in turn lead to improved product quality and reliability. A typical failure analysis is done through the topside of a package (i.e. a package that contains the integrated circuit) (topside analysis). However, as integrated circuits become more complex (i.e. as the minimum process features translation below 0.35 um and interconnect layers move beyond three layers) typical topside failure analysis become ineffective. One possible method of performing failure analysis on complex integrated circuits is with image based diagnostic tools designed to allow inspection through the backside of the silicon substrate of the integrated circuit. This backside analysis, however, is limited because the silicon, on the backside, has to be thinned (removed) to less than 100 microns while maintaining the circuit's functionality for the image based diagnostic tool to effectively evaluate the circuit. Moreover, in some advanced packages, used in the semiconductor industry, signal layers are used that pass beneath the silicon substrate. In order to gain access to the backside of the circuit, the aforementioned package signal layers must be removed. However, the removal of these signal layers would stop the circuit's functionality and thereby make the image based diagnostic tools ineffective.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and apparatus to conduct image based diagnostic analysis on the backside of relatively complex integrated circuit packages.